1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various semiconductor devices having a multiple nanowire channel structure and methods of variably connecting the nanowires for current density modulation purposes.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to the device described above, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20-nm CMOS technology node and beyond.
Another known transistor device is typically referred to as a nanowire device. In a nanowire device, at least the channel region of the device is comprised of one or more very small diameter, wire-like semiconductor structures. As with the other types of transistor devices discussed above, current flow through a nanowire device is controlled by controlling the voltage applied to the gate electrode. When an appropriate voltage is applied to the gate electrode, the channel region of the nanowire device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region, i.e., current flows through the nanowire structure. Persons skilled in the art will recognize that there are various known techniques that may be employed to manufacture such nanowire devices. Accordingly, the processing details for forming a basic nanowire device structure will not be described in detail herein.
There are several techniques by which electrical contact is made to the nanowire structures in the source/drain regions of a nanowire device. FIGS. 1A-1B depict one illustrative nanowire device 10 that will be referenced to describe one prior art technique for contacting the nanowires in the source/drain regions of the nanowire device 10. In general, the nanowire device 10 is formed above a layer of insulating material 12. In the depicted example, the nanowire device 10 includes first and second nanowires 14A, 14B, a schematically depicted gate structure 16 (that includes a gate insulation layer and a gate electrode), a gate cap layer 20 and sidewall spacers 22. When in operation, a channel region 18 will form in the portions of the nanowire structures 14A, 14B surrounded by the gate structure 16. Also depicted in FIGS. 1A-1B are illustrative source/drain connecting structures 30 that are formed in a layer of insulating material 24. In the embodiment shown in FIGS. 1A-1B, the source/drain connecting structures 30 are comprised of an epi semiconductor material 32 and a metal silicide region 34. Ultimately, conductive contacts (not shown) will be formed to make contact to the source/drain connecting structures 30.
FIGS. 2A-2B depict another illustrative nanowire device 11 that will be referenced to describe another prior art technique for contacting the nanowires in the source/drain regions of the nanowire device 11. In general, the nanowire device 11 has the same basic structure as that described above for the nanowire device 10. Thus, only certain differences will be noted for the nanowire device 11 relative to the nanowire device 10. In the nanowire device 11, after the gate structure 16, cap layer 20 and spacers 22 are formed, an epi semiconductor material 40 is formed around the exposed portions of the nanowires 14A, 14B, i.e., the portions positioned outside of the spacers 22. Thereafter, the layer of insulating material 24 is formed and patterned to define openings that expose portions of the nanowires 14A, 14B. In the nanowire device 11, the source/drain connecting structures 30 are comprised of a traditional contact metal 42, such as tungsten, that is deposited in the openings in the layer of insulating material 24.
In general, many if not all transistor devices are designed such that they can deliver the maximum performance, e.g., the maximum drive current, when needed by a particular circuit operating in a peak-demand situation or condition. However, in practice, an integrated circuit product does not continuously function in such peak-demand conditions. In practice, an integrated circuit product has periods of operation that fluctuate between full-performance, peak-demand requirements and lesser-performance requirements. Unfortunately, since the transistors are designed to operate for peak-demand conditions, they still produce the same amount of drive current even when the integrated circuit is operating in less than peak-demand situations. In short, there are times during the operation of an integrated circuit product that a “lower” performance transistor device, i.e., one producing a relatively lower drive current, would function equally as well as a higher performance transistor. Unfortunately, since the transistors are designed for peak-demand situations, there is no effective way to adjust or “tune” the drive current produced by the transistor based upon the then-current operational demands of the integrated circuit product. Accordingly, operating such high performance transistor devices during periods where the integrated circuit could function with a transistor that produces a lesser drive current represents an undesirable consumption of power. Conservation of power is particularly important in many mobile devices, e.g., cell phones, portable laptops, etc., so as to extend battery life.
The present disclosure is directed to various semiconductor devices having a multiple nanowire channel structure and methods of variably connecting the nanowires for current density modulation purposes that may solve or reduce one or more of the problems identified above.